Data converters are provided for receiving either an analog signal for conversion to a digital signal or a digital signal for conversion to analog signal. For conversion of analog signals to digital signals, an analog-to-digital converter is utilized. This is typically facilitated by sampling an analog voltage onto a capacitor array having a plurality of binary weighted capacitors. The capacitors then have the ability to have one plate thereof selectively switched between a reference voltage and ground to redistribute the charge among the capacitors, the switching done in a sequential manner in accordance with a successive approximation algorithm. By selectively switching the plates of the capacitors, and comparing the other plate of the capacitors, which is connected to a common input of a comparator, to a reference voltage, a digital value for the analog voltage sampled at the input can be determined.
A number of problems exist with the data conversion of an analog signal to a digital signal. Some of these problems reside in the various offsets of the inputs to the comparators, one of which is due to the fact that the actual chip ground may be different from the input ground at the PC board on which the actual chip is disposed. Additionally, the capacitors in the capacitor array are weighted and can have errors associated therewith. These errors can be accounted for by actually calibrating each of the capacitors with a sub-capacitor array. However, this calibration must be done at each power up of the A/D convertor. Additionally, these capacitor arrays can also have various parasitics associated therewith that effect the operation thereof and require the driving voltage to drive a higher capacitance value than that associated with the capacitance array.
When the capacitor arrays are operated in accordance with a data conversion algorithm such as a SAR algorithm, during the sampling period, the output node of the capacitor array is typically connected to an input of an amplifier and that input connected to a reference voltage. When operating in conjunction with a differential input amplifier, typically both input nodes thereof are switched to a common mode voltage during the sampling or tracking phase where the input voltage is impressed across the switched capacitors and then switched to the capacitor array thereafter. However, it is important when operating with a single array that noise introduction by the voltage source driving the common mode node or reference node for each of the inputs is cancelled. Unless these are balanced, there will be a noise contribution due to this reference voltage circuit.
After the SAR data conversion, the resulting digital value is locked into a latch, which information then comprises the results of the data conversion, i.e., the digital representation of the analog input value. This is then routed to data memory. In order to incorporate analog-to-digital data conversion circuitry on the same integrated circuit as digital processing circuitry, it is necessary to operate the data conversion circuitry virtually independent of the digital processing operation, so that an analog input signal can be continuously sampled at the same time as the digital processing circuitry is executing instructions. However, the two circuits will typically share a common memory, so that data collected by the data conversion circuitry can be digitally processed by the digital processing circuitry and there typically is only a single databus that allows access to this common memory, unless it is a dual port memory, a more complex and expensive solution. The reason to have a common memory is that the sampling operation with the data converter is operable to sample input signals in accordance with a predetermined sampling program and store this information in predetermined locations in the memory at substantially the same time as they are generated. The processing portion of the integrated circuit, while executing instructions, will in accordance with those instructions access certain locations of the memory for information regarding analog input signals that are sampled. For example, in a controller operation, there may be multiple sensor outputs that are measured on a periodic basis and stored in memory. When the processor desires information about the sensors, all it needs to do is look into the predetermined locations in the data memory. However, access to the data memory for information about the sampled analog values, or access to data memory for other reasons, must be managed to prevent data collisions on the data bus. Typically, a DMA is provided for hat function that, during a data conversion operation, will seize the bus and assert priority thereover at the end of a conversion cycle, wherein this information will be loaded into memory and the digital processing circuitry will be “halted” during that time. This can be a problem when multiple samples of information are collected and stored in the data memory, as once per conversion cycle the memory is blocked and the access by the digital processing circuitry is halted.